EMC testing of electricity meters using real-world and artificial current waveforms

In 2015, the energy measurement of some static electricity meters was found to be sensitive to specific conducted electromagnetic disturbances with very fast current changes caused by highly nonlinear loads, leading to meter errors up to several hundred percent. This article describes new results on the electromagnetic compatibility (EMC) of 16 different meters from all over Europe when exposed to real-world disturbance signals. Those test signals were obtained from household appliances and onsite measurements at metered supply points all over Europe. The results show that also the interference signals recorded onsite can cause measurement errors as large as several hundred percent, even for meters that pass the present EMC standards. This unambiguously demonstrates that the present immunity testing standards do not cover the most disturbing conducted interference occurring in present daily-life situations due to the increased use of nonlinear electronics. Furthermore, to enable the adoption of potential new test waveforms in future standards for electricity meter testing, artificial test waveforms were constructed based on real-world waveforms using a piece-wise linear model. These artificial test waveforms were demonstrated to cause meter errors similar to those caused by the original real-life waveforms they are representing, showing that they are suitable candidates for use in improved standardization of electricity meter testing.Postprint (published version

Interfacial properties of heterojunctions between transparent conductive oxides and silicon for solar cells

Thin films of transparent conductive oxides as active electrodes in combination with silicon substrates are pursued for new generation of solar cells. A main issue is to obtain structures with optimum interfacial properties in order to minimize charge carrier recombination and maximize cell efficiency. In this work we have investigated electronic properties and thermal stability of the interfacial states between indium tin oxide (ITO) and monocrystalline silicon. ITO films with thicknesses of 60 and 300 nm have been deposited by dc magnetron sputtering on n- and p-type (100) Si at room temperature. The samples were then annealed for 30 min at different temperatures in the range 100-600˚C. Current-voltage (IV), capacitance-voltage (CV) and deep-level transient spectroscopy (DLTS) have been used to electrically characterize the interface between ITO and Si. DLTS measurements on the samples with p-type Si reveal a dominant hole trap at around 0.37 eV above the valence band edge. In the n-type samples, several major electron traps have been observed in the range 0.1-0.2 eV below the conduction band edge. These electron traps are characterized by broad DLTS peaks indicating a broad band of the electronic energy levels rather than isolated point defect levels. All the traps in both p- and n-type samples are found to be located near the ITO-Si interface. Investigation of thermal stability of the observed electronic states has revealed that the dominant hole trap can be annealed out at 250˚C for 30 min, while the dominant electron traps can be stable up to 500˚C. IV and DLTS measurements demonstrate clear correlation between the annealing of the dominant electronic states and increase in the junction rectification

Electrical characterization of hydrogen-vacancy-related defects in monocrystalline silicon

Electrical characterization of point defects in silicon (Si) is carried out to study fundamental defects present in Si solar cell structures. The interactions between various defect complexes is investigated, while paying special attention to the interactions with hydrogen. As hydrogen is readily incorporated during manufacturing processes, it is important to learn about the defect dynamics of hydrogen related defects Firstly, hydrogen implantation into p- and n-type based pn-junctions has been investigated in order to learn about the fundamental nature of the defect reactions between vacancy related defects and hydrogen. Samples have been electrically characterized by capacitance–voltage (CV), deep level transient spectroscopy (DLTS) and minority carrier transient spectroscopy (MCTS), which reveals the presence of multiple hydrogen-related levels. A firm correlation between the reported donor and acceptor states of the vacancy–oxygen–hydrogen (VOH) complex is established in p-type samples, providing data on formation and annealing of both states. In the n-type samples, there is a rapid formation of a hydrogen-related level at Ec − 0.36 eV, at the expense of VO, without any formation of VOH after heat treatments at 200 C. This complex is not observed in the p-type samples, leading to the conclusion that the formation barrier for VOH must be higher in n-type than in p-type material. Further, an observation of a hydrogen-related defect in p-type samples, achieved by MCTS, provides preliminary data that may challenge the accepted model for the di–vacancy–hydrogen complex (V2H). The level observed in p-type samples,corresponds to a well-known DLTS peak in hydrogen contaminated n-type Si and is often ascribed to the acceptor level of V2H. However, the theoretically predicted single donor level of V2H is not observed in the investigated samples, thereby urging additional studies on the validity of the model of V2H. Finally, a study of interfaces between tin doped indium oxide (ITO) and silicon has been conducted. Thin films of ITO were sputtered onto crystalline pand n-type Si wafers, and a lithography process was applied to make individual diodes of various areas. By combining current–voltage (IV), CV and DLTS with secondary ion mass spectrometry (SIMS), a clear understanding of the composition and behavior of the interface is achieved. Heat treatments of the samples up to 600 C provide information of the defect evolution and the subsequent change in properties of the junction. The ITO/n-Si samples are found to be rectifying at all investigated temperatures, while the ITO/p-Si samples are rectifying up to 400 C, after which the junctions are transformed into an Ohmic behavior. Correlating these observations with the DLTS measurements reveals that the dominant hole traps anneal out as the rectification of the ITO/p-Si samples is at its highest. Likewise, the annealing of the dominant electron trap is followed by a significant increase in the rectification of the ITO/n-Si samples

Characterization of high-precision resistive voltage divider and buffer amplifier for ac voltage metrology

A high-precision voltage buffer and a 10:1 resistive voltage divider have been constructed for use in ac voltage and electrical power metrology. Long-term stability of the buffer's dc response has been demonstrated by two dc sweeps performed 20 days apart, with best-fit linearized gain varying less than 1 μV/V. The absolute ac gain has been measured using a high-precision digital multimeter for 10 Hz and 1 kHz with results consistent with dc within 5 μV/V. This value agrees with the characterization of ac–dc difference using thermal converters from different producers with a variety of resistance for various voltages from 1 V to 5 V. The ac–dc difference was further characterized better than 40 μV/V for the same voltages up to 100 kHz and better than 100 μV/V for 3 V at 1 MHz. Absolute ac gain and ac–dc difference has also been measured for the voltage divider and buffer combination from 10 V to 50 V, with similar agreement up to 1 kHz. The ac–dc difference from 10 Hz to 100 kHz of this combination shows an agreement well within 30 μV/V in this entire voltage span with a total response not exceeding 125 μV/V. This make the voltage divider and buffer combination suitable for sampling electrical powers for a wide range of voltages

Characterization of high-precision resistive voltage divider and buffer amplifier for ac voltage metrology

A high-precision voltage buffer and a 10:1 resistive voltage divider have been constructed for use in ac voltage and electrical power metrology. Long-term stability of the buffer's dc response has been demonstrated by two dc sweeps performed 20 days apart, with best-fit linearized gain varying less than 1 μV/V. The absolute ac gain has been measured using a high-precision digital multimeter for 10 Hz and 1 kHz with results consistent with dc within 5 μV/V. This value agrees with the characterization of ac–dc difference using thermal converters from different producers with a variety of resistance for various voltages from 1 V to 5 V. The ac–dc difference was further characterized better than 40 μV/V for the same voltages up to 100 kHz and better than 100 μV/V for 3 V at 1 MHz. Absolute ac gain and ac–dc difference has also been measured for the voltage divider and buffer combination from 10 V to 50 V, with similar agreement up to 1 kHz. The ac–dc difference from 10 Hz to 100 kHz of this combination shows an agreement well within 30 μV/V in this entire voltage span with a total response not exceeding 125 μV/V. This make the voltage divider and buffer combination suitable for sampling electrical powers for a wide range of voltages

Evaluation of InGaAs/InP photodiode for high-speed operation at 4 K

An optically controlled high-speed current source located at 4 K is likely to improve the performance of pulse-driven Josephson junction arrays. A custom photodiode module with an Albis PDCS24L InGaAs/InP PIN photodiode is investigated in order to determine the suitability at 4 K. The DC and frequency response were tested at room temperature and at temperatures down to 4 K. For continuous wave optical input, photocurrents above 15 mA were produced at both room temperature and 4 K. I–V measurements show that the threshold voltage increased from 0.5 V at room temperature to 0.8 V at 4 K. The transmission coefficient S21 of the optoelectronic system, including cables and modulated laser source, was measured using a vector network analyzer. Up to 14 GHz, the results showed that the frequency response at 4 K was not degraded compared to room temperature. At room temperature, reverse bias voltages of up to 3 V was required for the highest bandwidth, while at 4 K, the photodiode was operated at nearly full speed even at 0 V reverse bias

Evaluation of InGaAs/InP photodiode for high-speed operation at 4 K

An optically controlled high-speed current source located at 4 K is likely to improve the performance of pulse-driven Josephson junction arrays. A custom photodiode module with an Albis PDCS24L InGaAs/InP PIN photodiode is investigated in order to determine the suitability at 4 K. The DC and frequency response were tested at room temperature and at temperatures down to 4 K. For continuous wave optical input, photocurrents above 15 mA were produced at both room temperature and 4 K. I–V measurements show that the threshold voltage increased from 0.5 V at room temperature to 0.8 V at 4 K. The transmission coefficient S21 of the optoelectronic system, including cables and modulated laser source, was measured using a vector network analyzer. Up to 14 GHz, the results showed that the frequency response at 4 K was not degraded compared to room temperature. At room temperature, reverse bias voltages of up to 3 V was required for the highest bandwidth, while at 4 K, the photodiode was operated at nearly full speed even at 0 V reverse bias